PXS20RM Datasheet, PDF (1008/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

LIN Controller (LINFlexD)
Field
FEF
BOF
NF
Table 31-16. LINESR field descriptions (continued)
Description
Framing Error Flag
This bit is set by hardware and indicates to the software that LINFlexD has detected a framing error
(invalid stop bit). This error can occur during reception of any data in the response field (Master or
Slave mode) or during reception of Synch Field or Identifier Field in Slave mode.
Buffer Overrun Flag
This bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. If
RBLM in LINCR1 is set then the new byte received is discarded. If RBLM is reset then the new byte
overwrites the buffer. It can be cleared by software.
Noise Flag
This bit is set by hardware when noise is detected on a received character. This bit is cleared by
software.
31.10.5 UART mode control register (UARTCR)
Offset: 0x10
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
TDFLTFC¹
W
RDFLRFC¹
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 _{These fields are read/write in UART buffer mode and read-only in other modes.}
2 _{These fields are writable only in Initialization mode (LINCR1[INIT] = 1).}
Figure 31-22. UART mode control register (UARTCR)
31-32
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor