PXS20RM Datasheet, PDF (1038/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

LIN Controller (LINFlexD)
Table 31-45. TCD settings (slave node, TX mode)
TCD field
CITER[14:0]
BITER[14:0]
NBYTES[31:0]
Value
1
1
4/8 = N
SADDR[31:0]
SOFF[15:0]
SSIZE[2:0]
SLAST[31:0]
DADDR[31:0]
DOFF[15:0]
DSIZE[2:0]
DLAST_SGA[31:0]
INT_MAJ
D_REQ
START
RAM address
4
2
–N
BDRL address
4
2
–N
0/1
1
0
Description
Single iteration for the “major” loop
Single iteration for the “major” loop
Data buffer is stuffed with dummy bytes if the length is not
word aligned.
BDRL + BDRM
Word increment
Word transfer
Word increment
Word transfer
No scatter/gather processing
Interrupt disabled/enabled
Only on the last TCD of the chain.
No software request
31.11.4 Slave node, RX mode
On a slave node in RX mode, the DMA interface requires a DMA RX channel for each ID filter
programmed in RX mode. In case a single DMA RX channel is available, a single ID field filter must be
programmed in RX mode. Each TCD controls a single frame, except for the extended frames (multiple
TCDs). The memory map associated to the TCD chain (RAM area and LINFlexD registers) is shown in
Figure 31-49.
LINFlex2 registers
RAM area
Frame (n)
Master –> Slave
Slave –> Slave
BIDR (4 bytes)
BDRL + BDRM
(4/8 bytes)
DMA transfer
BIDR (4 bytes)
BDRL + BDRM
(4/8 bytes)
TCD (n)
Extended
Frame (n+1)
BIDR (4 bytes)
BDRL + BDRM
(8 bytes)
BIDR (4 bytes)
BDRL + BDRM
(8 bytes)
TCD (n+1)
Linked chain
Extended
Frame (n+2)
BDRL + BDRM
(4/8 bytes)
BDRL + BDRM
(4/8 bytes)
1 DMA RX channel/filter (TCD single and/or linked chain)
Figure 31-49. TCD chain memory map (slave node, RX mode)
TCD (n+2)
The TCD chain of the DMA RX channel on a slave node supports:
31-62
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor