PXS20RM Datasheet, PDF (477/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
21.4.2.1 Processor Core Type (PCT) register
The PCT is a 16-bit read-only register specifying the architecture of the processor core in the device. The
state of this register is defined by a module input signal; it can only be read from the IPS programming
model. Any attempted write is ignored.
See Figure 21-1 and Table 21-2 for the Processor Core Type definition.
Register address: ECSM Base + 0x0000
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
PCT
W
RESET: 1
1
1
0
0
1
0
0
0
1
0
0
0
1
1
0
Name
PCT
= Unimplemented
Figure 21-1. Processor Core Type (PCT) Register
Table 21-2. Processor Core Type (PCT) Field Descriptions
Description
Processor Core Type
0xE446: e200z4d Power Architecture core
21.4.2.2 Chip-Defined Platform Revision (REV) register
The REV is a 16-bit read-only register specifying a revision number. The state of this register is defined
by an input signal; it can only be read from the IPS programming model. Any attempted write is ignored.
See Figure 21-2 and Table 21-3 for the REV definition.
Register address: ECSM Base + 0x0002
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
PLREV
W
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Field
PLREV
= Unimplemented
Figure 21-2. Chip-Defined Platform Revision (REV) Register
Table 21-3. REV field descriptions
Description
Revision
This field is specified by an input signal to define a software-visible revision number.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
21-3