PXS20RM Datasheet, PDF (609/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexCAN Module
1 = Indicates the current MB has a Remote Frame to be transmitted
0 = Indicates the current MB has a Data Frame to be transmitted
LENGTH — Length of Data in Bytes
This 4-bit field is the length (in bytes) of the Rx or Tx data, which is located in offset 0x8 through 0xF
of the MB space (see Figure 24-2). In reception, this field is written by the FlexCAN module, copied
from the DLC (Data Length Code) field of the received frame. In transmission, this field is written by
the CPU and corresponds to the DLC field value of the frame to be transmitted. When RTR=1, the
Frame to be transmitted is a Remote Frame and does not include the data field, regardless of the Length
field.
TIME STAMP — Free-Running Counter Time Stamp
This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when
the beginning of the Identifier field appears on the CAN bus.
PRIO — Local priority
This 3-bit field is only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers.
These bits are not transmitted. They are appended to the regular ID to define the transmission priority.
See Section 24.4.3, Arbitration process.
ID — Frame Identifier
In Standard Frame format, only the 11 most significant bits (3 to 13) are used for frame identification
in both receive and transmit cases. The 18 least significant bits are ignored. In Extended Frame format,
all bits are used for frame identification in both receive and transmit cases.
DATA — Data Field
Up to eight bytes can be used for a data frame. For Rx frames, the data is stored as it is received from
the CAN bus. For Tx frames, the CPU prepares the data field to be transmitted within the frame.
24.3.3 Rx FIFO Structure
When the FEN bit is set in the MCR, the memory area from 0x80 to 0xFC (which is normally occupied by
MBs 0 to 7) is used by the reception FIFO engine. Figure 24-3 shows the Rx FIFO data structure. The
region 0x80-0x8C contains an MB structure which is the port through which the CPU reads data from the
FIFO (the oldest frame received and not read yet). The region 0x90-0xDC is reserved for internal use of
the FIFO engine. The region 0xE0-0xFC contains an 8-entry ID table that specifies filtering criteria for
accepting frames into the FIFO. Figure 24-4 shows the three different formats that the elements of the ID
table can assume, depending on the IDAM field of the MCR. Note that all elements of the table must have
the same format. See Section 24.4.7, Rx FIFO, for more information.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
24-9