PXS20RM Datasheet, PDF (161/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Table 9-2. ADC memory map (continued)
Address offset
Register
0x0CC–0x0FC
0x100
0x104
0x108
0x10C
0x110
0x114
0x118
0x11C
0x120
0x124
0x128
0x12C
0x130
0x134
0x138
0x13C
0x140–0x280
0x280
0x284
0x288
0x28C
0x290
0x294
0x298
0x29C
0x2A0
0x2A4
0x2A8
0x2AC
0x2B0
0x2B4
0x2B8–0x2DC
Reserved
Channel 0 Data Register (CDR0)
Channel 1 Data Register (CDR1)
Channel 2 Data Register (CDR2)
Channel 3 Data Register (CDR3)
Channel 4 Data Register (CDR4)
Channel 5 Data Register (CDR5)
Channel 6 Data Register (CDR6)
Channel 7 Data Register (CDR7)
Channel 8 Data Register (CDR8)
Channel 9 Data Register (CDR9)
Channel 10 Data Register (CDR10)
Channel 11 Data Register (CDR11)
Channel 12 Data Register (CDR12)
Channel 13 Data Register (CDR13)
Channel 14 Data Register (CDR14)
Channel 15 Data Register (CDR15)
Reserved
Threshold Register 4 (THRHLR4)
Threshold Register 5 (THRHLR5)
Threshold Register 6 (THRHLR6)
Threshold Register 7 (THRHLR7)
Threshold Register 8 (THRHLR8)
Threshold Register 9 (THRHLR9)
Threshold Register 10 (THRHLR10)
Threshold Register 11 (THRHLR11)
Threshold Register 12 (THRHLR12)
Threshold Register 13 (THRHLR13)
Threshold Register 14 (THRHLR14)
Threshold Register 15 (THRHLR15)
Channel Watchdog Selection Register 0 (CWSEL0)
Channel Watchdog Selection Register 1 (CWSEL1)
Reserved
Analog-to-Digital Converter (ADC)
Location
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PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
9-3