PXS20RM Datasheet, PDF (707/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flexible Motor Control Pulse Width Modulator Module (FlexPWM)
0 = Normal mode. PWM outputs disabled by this fault are not enabled until the FFLAGx bit is clear
at the start of a half cycle or full cycle depending on the state of the FFULL bits without regard
to the state of the FFPINx bit. The PWM outputs disabled by this fault input will not be
re-enabled until the actual FAULTx input signal de-asserts since the fault input will
combinationally disable the PWM outputs (as programmed in DISMAP).
NOTE
The FFPINx bit may indicate a fault condition still exists even though the
actual fault signal at the FAULTx pin is clear due to the fault filter latency.
FIE - Fault Interrupt Enables
This read/write bit enables CPU interrupt requests generated by the FAULTx pins. A reset clears FIE.
1 = FAULTx CPU interrupt requests enabled.
0 = FAULTx CPU interrupt requests disabled.
NOTE
The fault protection circuit is independent of the FIEx bit and is always
active. If a fault is detected, the PWM outputs are disabled according to the
disable mapping register.
25.4.5.2 Fault Status Register (FSTS)
PWM_BASE
+$14E
0
1
2
3
4 5 6 7 8 9 10 11 12 13 14 15
Read
Write
000
FTEST
FFPIN
FFULL
FFLAG
Reset
000
0
111100001111
Figure 25-65. Fault Status Register (FSTS)
FTEST - Fault Test
These read/write bit is used to simulate a fault condition. Setting this bit will cause a simulated fault
to be sent into all of the fault filters. The condition will propagate to the fault flags and possibly the
PWM outputs depending on the DISMAP settings. Clearing this bit removes the simulated fault
condition.
1 = Cause a simulated fault.
0 = No fault.
FFPIN - Filtered Fault Pins
These read-only bits reflect the current state of the filtered FAULTx pins converted to high polarity.
A logic 1 indicates a fault condition exists on the filtered FAULTx pin. A reset has no effect on FFPIN.
FFULL - Full Cycle
These read/write bits are used to control the timing for re-enabling the PWM outputs after a fault
condition. These bits apply to both automatic and manual clearing of a fault condition.
1 = PWM outputs are re-enabled only at the start of a full cycle.
0 = PWM outputs are re-enabled at the start of a full or half cycle.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
25-61