PXS20RM Datasheet, PDF (526/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Fault Collection and Control Unit (FCCU)
Offset: 0x0E0
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0000000000000
W
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-22. FCCU IRQ Status Register (FCCU_IRQ_STAT)
Table 22-21. FCCU_IRQ_STAT field descriptions
Field
CFG_TO_STAT Configuration Time-out Status
0: No configuration time-out error
1: Configuration time-out error
Description
ALRM_STAT
This bit can be read and cleared by the software.
Alarm Interrupt Status
0: Alarm interrupt is OFF
1: Alarm interrupt is ON
NMI_STAT
This bit can be only read by the software.
NMI Interrupt Status
0: NMI interrupt is OFF
1: NMI interrupt is ON
This bit can be only read by the software.
22.6.20 FCCU IRQ Enable Register (FCCU_IRQ_EN)
The FCCU_IRQ_EN register defines the FCCU interrupt enable register related to the following events:
• Configuration time-out error
The external interrupt is asserted if any interrupt status bit of the FCCU_IRQ_STAT is set and the
respective enable bit of the FCCU_IRQ_EN register is also set.
22-26
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor