PXS20RM Datasheet, PDF (1178/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Power Management Unit (PMU)
Address: Base + 0x70
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
MF_BB
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 39-5. PMUCTRL mask fault register (PMUCTRL_MASKF)
Table 39-6. PMUCTRL_MASKF field descriptions
Field
MF_BB
Description
Mask Fault Bypass Ballast. This field defines the mask for the nBYPASS_BALLAST_LV[3:0]
bus.
0 MF_BB[n], means BYPASS_BALLAST_LV[n] = ‘0’; where n goes from 3 down to 0.
1 MF_BB[n], means BYPASS_BALLAST_LV[n] = NOT nBYPASS_BALLAST_LV[n]; where n goes
from 3 down to 0.
39.7.4 PMUCTRL fault monitor register (PMUCTRL_FAULT)
Address: Base + 0x74
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
BB_LV
0
0
0
0
0
0
0
0
0
W
Reset ₁
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R₀
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 39-6. PMUCTRL fault monitor register (PMUCTRL_FAULT)
39-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor