PXS20RM Datasheet, PDF (585/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Address
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
0x0060
0x0064
0x0068
Table 23-24. Test flash information (continued)
Word name
Function
ADC0_CAL W3
ADC0_CAL W4
ADC0_CAL W5
ADC0_CAL W6
ADC0_CAL W7
ADC0_CAL W8
ADC0 Reserved
ADC0 Self-Test calibration
ADC0 Self-Test calibration
ADC0 Self-Test calibration
ADC0 Self-Test calibration
ADC0 Self-Test calibration
ADC0 Self-Test calibration
ADC0 reserved
ADC1_CAL W1
ADC1_CAL W2
ADC1_CAL W3
ADC1_CAL W4
ADC1_CAL W5
ADC1_CAL W6
ADC1_CAL W7
ADC1_CAL W8
ADC1 Reserved
ADC1 Self-Test calibration
ADC1 Self-Test calibration
ADC1 Self-Test calibration
ADC1 Self-Test calibration
ADC1 Self-Test calibration
ADC1 Self-Test calibration
ADC1 Self-Test calibration
ADC1 Self-Test calibration
ADC1 Reserved
PART ID1 Low
PART ID1 High
PART ID2
SPARE 1
SPARE 2
Plant and Lot Number ASCII format
Plant and Lot Number ASCII format
Wafer number and coordinates
Reserved
Reserved
Flash Memory
Note
2x12bits words
2x12bits words
2x12bits words
2x12bits words
2x12bits words
2x12bits words
For future
expansion
2x12bits words
2x12bits words
2x12bits words
2x12bits words
2x12bits words
2x12bits words
2x12bits words
2x12bits words
For future
expansion
Needed for KGD
Needed for KGD
Needed for KGD
For future usage
For future usage
23.2 Dual-ported platform flash memory controller (PFLASH2P)
23.2.1 Introduction
This section provides an overview of the Dual Ported Platform Flash Controller (PFLASH2P) for Standard
Product Platforms (SPP). The PFLASH2P acts as an interface between the system bus (AHB-Lite 2.v6)
and the integrated flash memory array. It intelligently converts the protocols between the system bus and
the dedicated flash array interface.
The PFLASH2P block supports a 64-bit data bus width at the AHB ports, and a 128-bit read data interface
from the flash memory array. The PFLASH2P has two AHB ports with dedicated line buffers for each
interface. Each port has four, 128-bit line buffers and an associated controller which prefetches sequential
lines of data from the flash array into the buffers. Line buffer hits support zero-wait AHB data phase
responses. AHB read requests which miss the buffers generate the needed flash array access and are
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
23-35