PXS20RM Datasheet, PDF (665/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flexible Motor Control Pulse Width Modulator Module (FlexPWM)
The generation of the Local Sync signal is performed exactly the same way as the other PWM signals in
the submodule. While comparator 0 causes a rising edge of the Local Sync signal, comparator 1 generates
a falling edge. Comparator 1 is also hardwired to the reload logic to generate the half cycle reload
indicator.
If VAL1 is controlling the modulus of the counter and VAL0 is half of the VAL1 register minus the INIT
value, then the half cycle reload pulse will occur exactly half way through the timer count period and the
Local Sync will have a 50% duty cycle. On the other hand, if the VAL1 and VAL0 registers are not
required for register reloading or counter initialization, they can be used to modulate the duty cycle of the
Local Sync signal effectively turning it into an auxiliary PWM signal (PWMX) assuming that the PWMX
pin is not being used for another function such as input capture or deadtime distortion correction.
Including the Local Sync signal, each submodule is capable of generating 3 PWM signals where software
has complete control over each edge of each of the signals.
If the comparators and edge value registers are not required for PWM generation, they can also be used
for other functions such as output compares, generating output triggers, or generating interrupts at timed
intervals.
The 16-bit comparators shown in Figure 25-16 are "equal to or greater than" not just "equal to"
comparators. In addition, if both the set and reset of the flip-flop are both asserted, then the flop output
goes to 0.
25.3.3.5 Output compare capabilities
By using the VALx registers in conjunction with the submodule timer and 16 bit comparators, buffered
output compare functionality can be achieved with no additional hardware required. Specifically, the
following output compare functions are possible:
• An output compare sets the output high
• An output compare sets the output low
• An output compare generates an interrupt
• An output compare generates an output trigger
Referring again to Figure 25-16, an output compare is initiated by programming a VALx register for a
timer compare which in turn causes the output of the D flip-flop to either set or reset. For example, if an
output compare is desired on the PWMA signal that sets it high, VAL2 would be programmed with the
counter value where the output compare should take place. However, to prevent the D flip-flop from being
reset again after the compare has occurred, the VAL3 register must be programmed to a value outside of
the modulus range of the counter. Therefore, a compare that would result in resetting the D flip-flop output
would never occur. Conversely, if an output compare is desired on the PWMA signal that sets it low, the
VAL3 register is programmed with the appropriate count value and the VAL2 register is programmed with
a value outside the counter modulus range. Regardless of whether a high compare or low compare is
programmed, an interrupt or output trigger can be generated when the compare event occurs.
25.3.3.6 Force out logic
For each submodule software can select between seven signal sources for the FORCE_OUT signal: the
local FORCE bit, the Master Force signal from submodule0, the local Reload signal, the Master Reload
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
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