PXS20RM Datasheet, PDF (1249/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Reset Generation Module (MC_RGM)
NOTE
This could be useful for fast reset sequence, for example to skip flash reset.
It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read in user
mode.
Table 41-8. Functional Event Short Sequence Register (RGM_FESS) Field Descriptions
Field
Description
SS_EXR
Short Sequence for External Reset
0 The reset sequence triggered by an external reset event will start from PHASE1
1 The reset sequence triggered by an external reset event will start from PHASE3, skipping
PHASE1 and PHASE2
SS_FCCU_H Short Sequence for FCCU hard reaction request
ARD
0 The reset sequence triggered by a FCCU hard reaction request event will start from PHASE1
SS_FCCU_S Short Sequence for FCCU soft reaction request
OFT
1 The reset sequence triggered by a FCCU soft reaction request event will start from PHASE3,
skipping PHASE1 and PHASE2
SS_ST_DON Short Sequence for self-test completed
E
0 The reset sequence triggered by a self-test completed event will start from PHASE1
SS_CMU12_ Short Sequence for CMU1/2 clock freq. too high/low
FHL
0 The reset sequence triggered by a CMU1/2 clock freq. too high/low event will start from PHASE1
1 The reset sequence triggered by a CMU1/2 clock freq. too high/low event will start from PHASE3,
skipping PHASE1 and PHASE2
SS_FL_ECC Short Sequence for flash, ECC, or lock-step error
_RCC 0 The reset sequence triggered by a flash, ECC, or lock-step error event will start from PHASE1
SS_PLL1
Short Sequence for PLL1 fail
0 The reset sequence triggered by a PLL1 fail event will start from PHASE1
1 The reset sequence triggered by a PLL1 fail event will start from PHASE3, skipping PHASE1 and
PHASE2
SS_SWT Short Sequence for software watchdog timer
0 The reset sequence triggered by a software watchdog timer event will start from PHASE1
SS_CMU0_F Short Sequence for system clock freq. too high/low
HL
0 The reset sequence triggered by a system clock freq. too high/low event will start from PHASE1
1 The reset sequence triggered by a system clock freq. too high/low event will start from PHASE3,
skipping PHASE1 and PHASE2
SS_CMU0_
OLR
Short Sequence for oscillator freq. too low
0 The reset sequence triggered by a oscillator freq. too low event will start from PHASE1
1 The reset sequence triggered by a oscillator freq. too low event will start from PHASE3, skipping
PHASE1 and PHASE2
SS_PLL0
Short Sequence for PLL0 fail
0 The reset sequence triggered by a PLL0 fail event will start from PHASE1
1 The reset sequence triggered by a PLL0 fail event will start from PHASE3, skipping PHASE1 and
PHASE2
SS_CWD
Short Sequence for core watchdog reset
0 The reset sequence triggered by a core watchdog reset event will start from PHASE1
1 The reset sequence triggered by a core watchdog reset event will start from PHASE3, skipping
PHASE1 and PHASE2
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
41-17