PXS20RM Datasheet, PDF (351/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Attributes Registers 0–3 (DSPI_CTAR0–DSPI_CTAR3)) select the frequency of SCK by the formula in
the BR field description. Table 16-18 shows an example of how to compute the baud rate.
Table 16-18. Baud Rate Computation Example
f_sys
100 MHz
20 MHz
PBR
0b00
0b00
Prescaler
2
2
BR
0b0000
0b0000
Scaler
2
2
DBR
0
1
Baud Rate
25 Mb/s
10 Mb/s
16.4.3.2 PCS to SCK Delay (t_CSC)
The PCS to SCK delay is the length of time from assertion of the PCS signal to the first SCK edge. See
Figure 16-23 for an illustration of the PCS to SCK delay. The PCSSCK and CSSCK fields in the
DSPI_CTARx registers select the PCS to SCK delay by the formula in the CSSCK field description (see
Section 16.3.2.4, DSPI Clock and Transfer Attributes Registers 0–3 (DSPI_CTAR0–DSPI_CTAR3)).
Table 16-19 shows an example of how to compute the PCS to SCK delay.
Table 16-19. PCS to SCK Delay Computation Example
f_sys
100 MHz
PCSSCK
0b01
Prescaler
3
CSSCK
0b0100
Scaler
32
PCS to SCK Delay
0.96 s
16.4.3.3 After SCK Delay (t_ASC)
The After SCK Delay is the length of time between the last edge of SCK and the negation of PCS. See
Figure 16-23 and Figure 16-24 for illustrations of the After SCK delay. The PASC and ASC fields in the
DSPI_CTARx registers select the After SCK Delay by the formula in the ASC field description (see
Section 16.3.2.4, DSPI Clock and Transfer Attributes Registers 0–3 (DSPI_CTAR0–DSPI_CTAR3)).
Table 16-20 shows an example of how to compute the After SCK delay.
Table 16-20. After SCK Delay Computation Example
f_sys
100 MHz
PASC
0b01
Prescaler
3
ASC
0b0100
Scaler
32
After SCK Delay
0.96 s
16.4.3.4 Delay after Transfer (t_DT)
The Delay after Transfer is the minimum time between negation of the PCS signal for a frame and the
assertion of the PCS signal for the next frame. See Figure 16-23 for an illustration of the Delay after
Transfer. The PDT and DT fields in the DSPI_CTARx registers select the Delay after Transfer by the
formula in the DT field description (see Section 16.3.2.4, DSPI Clock and Transfer Attributes Registers
0–3 (DSPI_CTAR0–DSPI_CTAR3)). Table 16-21 shows an example of how to compute the Delay after
Transfer.
Table 16-21. Delay after Transfer Computation Example
f_sys
100 MHz
PDT
0b01
Prescaler
3
DT
0b1110
Scaler
32768
Delay after Transfer
0.98 ms
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
16-31