PXS20RM Datasheet, PDF (542/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Fault Collection and Control Unit (FCCU)
Two modes, depending on the FCCU_CFG.CM bit setting, can be programmed to define the FCCU_F
protocol in CONFIG state:
• configuration labelling: the CONFIG state is marked by a specific FCCU_F setting
• configuration transparency: the CONFIG and NORMAL state are equivalent
The FCCU_F frequency is programmable based on the IRCOSC clock frequency divided by a fixed
prescaler (1024).
The external monitor of the FCCU_F protocol should oversample the FCCU_F signals in order to
synchronize periodically the external clock (used by the monitor) and the IRCOSC clock detecting the
edge transition of the FCCU_F protocol in dual-rail or time-switching mode.
NOTE
The initial values, after the reset phase, of the FCCU_CFG.CM,
FCCU_CFG.SM, FCCU_CFG.PS, FCCU_CFG.FOP, FCCU_CFG.FOM
registers are set by the NVM interface (see Section 22.7.9, NVM interface).
22.7.10.1 Dual-rail protocol
Dual-rail encoding is an alternate method for encoding bits. In contrast with classical encoding, where
each signal carries a single-bit value, dual-rail encoded circuits use two wires to carry each bit. The
encoding scheme is given in Table 22-28 and the related timing diagram is given in Figure 22-40 and
Figure 22-41.
Table 22-28. Dual-rail encoding
Logical state
non-faulty
non-faulty
faulty
faulty
reset
configuration
Dual-rail encoding
(output pins FCCU_F[1:0])
Note
10
01
00
11
high-Z
high-Z
= non-faulty
toggling
toggling
no toggling
when FCCU_CFG.CM = 0
when FCCU_CFG.CM = 1
As long as FCCU is in NORMAL or ALARM state, output will show “no-faulty“signal. Output pins
FCCU_F[0] and FCCU_F[1] will toggle between 01 and 10 with a given frequency. By default the
frequency is the IRCOSC clock frequency divided by 18*1024.
During the RESET phase and during self testing the output pins are set as “high impedance”.
NOTE
Figure 22-40 and Figure 22-41 are formatted to display the behavior in all
four phases (reset, normal, error, and config), not to imply transitions
between one phase to another. In particular, transition from error phase to
config phase is not possible.
22-42
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor