PXS20RM Datasheet, PDF (742/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
Table 26-20. FR_PIER0 field descriptions
Field
Description
MTX_IE
LTXB_IE
LTXA_IE
TBVB_IE
TBVA_IE
TI2_IE
TI1_IE
CYS_IE
Media Access Test Symbol Received Interrupt Enable — This bit controls MTX_IF interrupt
request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
pLatestTx Violation on Channel B Interrupt Enable — This bit controls LTXB_IF interrupt
request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
pLatestTx Violation on Channel A Interrupt Enable — This bit controls LTXA_IF interrupt
request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Transmission across boundary on channel B Interrupt Enable — This bit controls TBVB_IF
interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Transmission across boundary on channel A Interrupt Enable — This bit controls TBVA_IF
interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Timer 2 Expired Interrupt Enable — This bit controls TI1_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Timer 1 Expired Interrupt Enable — This bit controls TI1_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Cycle Start Interrupt Enable — This bit controls CYC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
26.5.2.16 Protocol Interrupt Enable Register 1 (FR_PIER1)
Base + 0x001E
Write: Anytime
0
1
2
3
4
5
6
7
8
R _{EMC IPC PECF PSC SSI3 SSI2 SSI1 SSI0} 0
W ^{_IE _IE _IE _IE _IE _IE _IE _IE}
9
10
11
12
13
14
15
0 _{EVT ODT} 0
0
0
0
_IE _IE
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-16. Protocol Interrupt Enable Register 1 (FR_PIER1)
This register defines whether or not the individual interrupt flags defined in Protocol Interrupt Flag
Register 1 (FR_PIFR1) can generate a protocol interrupt request.
26-30
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor