PXS20RM Datasheet, PDF (941/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Chapter 29
JTAG Controller (JTAGC)
29.1 Introduction
Figure 29-1 is a block diagram of the JTAG Controller (JTAGC) block.
JTAG Controller (JTAGC)
TMS
TCK
.
._{. TDI}
.
.
JCOMP
Test Access Port (TAP)
Controller
1-Bit Bypass Register
32-Bit Device Identification Register
Boundary Scan Register
5-Bit TAP Instruction Decoder
TDO
.
5-Bit TAP Instruction Decoder
.
5-Bit TAP Instruction Register
Figure 29-1. JTAG STL (IEEE 1149.1) block diagram
29.1.1 Overview
The JTAGC block provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as
defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is
communicated in serial format.
29.1.2 Features
The JTAGC block is compliant with the IEEE 1149.1-2001 standard, and supports the following features:
• IEEE 1149.1-2001 Test Access Port (TAP) interface
— 4 pins (TDI, TMS, TCK, and TDO)
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
29-1