PXS20RM Datasheet, PDF (1033/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

LIN Controller (LINFlexD)
Table 31-42. TCD settings (master node, TX mode)
TCD field
CITER[14:0]
BITER[14:0]
NBYTES[31:0]
SADDR[31:0]
SOFF[15:0]
SSIZE[2:0]
SLAST[31:0]
DADDR[31:0]
DOFF[15:0]
DSIZE[2:0]
DLAST_SGA[31:0]
INT_MAJ
D_REQ
START
Value
Description
1
Single iteration for the “major” loop
1
Single iteration for the “major” loop
[4 + 4] + 0/4/8 = N Data buffer is stuffed with dummy bytes if the length is not
word aligned.
LINCR2 + BIDR + BDRL + BDRM
RAM address
4
Word increment
2
Word transfer
–N
LINCR2 address
4
Word increment
2
Word transfer
–N
No scatter/gather processing
0/1
Interrupt disabled/enabled
1
Only on the last TCD of the chain.
0
No software request
31.11.2 Master node, RX mode
On a master node in RX mode, the DMA interface requires a single RX channel. Each TCD controls a
single frame, except for the extended frames (multiple TCDs). The memory map associated to the TCD
chain (RAM area and LINFlexD registers) is shown in Figure 31-45.
Frame (n)
Slave –> Master
LINFlex2 registers
BIDR (4 bytes)
BDRL + BDRM
(4/8 bytes)
DMA transfer
RAM area
BIDR (4 bytes)
BDRL + BDRM
(4/8 bytes)
TCD (n)
Extended
Frame (n+1)
BIDR (4 bytes)
BDRL + BDRM
(8 bytes)
BIDR (4 bytes)
BDRL + BDRM
(8 bytes)
TCD (n+1)
Linked chain
Extended
Frame (n+2)
BDRL + BDRM
(4/8 bytes)
BDRL + BDRM
(4/8 bytes)
1 DMA RX channel (TCD single and/or linked chain)
Figure 31-45. TCD chain memory map (master node, RX mode)
TCD (n+2)
The TCD chain of the DMA Rx channel on a master node supports Slave-to-Master reception of the data
field.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
31-57