PXS20RM Datasheet, PDF (166/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
9.3.3 Interrupt registers
9.3.3.1 Interrupt Status Register (ISR)
The Interrupt Status Register (ISR) contains interrupt status bits for the ADC.
Address: Base + 0x010
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0000000000
JEO
C
JEC
H
EOC ECH
W w1c
w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-3. Interrupt Status Register (ISR)
Table 9-5. ISR field descriptions
Field
Description
REF_RANGE
EOCTU
JEOC
JECH
EOC
ECH
This bit is set if REF_RANGE output from the ADC does not match with the expected value
programmed in the MCR.
End of CTU Conversion interrupt flag. It is the interrupt of the digital end of conversion for the CTU
channel; active when set. When this bit is set, an EOCTU interrupt has occurred.
End of Injected Channel Conversion interrupt flag. It is the interrupt of the digital end of conversion
for the injected channel; active when set. When this bit is set, a JEOC interrupt has occurred.
End of Injected Chain Conversion interrupt flag. It is the interrupt of the digital end of chain
conversion for the injected channel; active when set. When this bit is set, a JECH interrupt has
occurred.
End of Channel Conversion interrupt flag. It is the interrupt of the digital end of conversion. When
this bit is set, an EOC interrupt has occurred.
End of Chain Conversion interrupt flag. It is the interrupt of the digital end of chain conversion.
When this bit is set, an ECH interrupt has occurred.
9.3.3.2 Channel Pending Register 0 (CEOCFR0)
PXS20 Microcontroller Reference Manual, Rev. 1
9-8
Freescale Semiconductor