PXS20RM Datasheet, PDF (875/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
The behavior of the CC after the occurrence of a system bus failure is defined by the SBFF bit in the
Module Configuration Register (FR_MCR).
26.6.19.1 System Bus Illegal Address Access
If the system bus detects an CC access to an illegal address, the CC receives a notification from the system
bus about this event and sets the ILSA_EF flag in the CHI Error Flag Register (FR_CHIERFR).
26.6.19.2 System Bus Access Timeout
The CC starts a timer when it has send an access request to the system bus. This timer expires after 2 *
FR_SYMATOR[TIMEOUT] + 2 system bus clock cycles. If the access is not finished within this amount
of time, the SBCF_EF flag in the CHI Error Flag Register (FR_CHIERFR) is set.
NOTE
The value of the TIMEOUT field should be set to greater than 1. For the
value 1 and 0, a system bus access timeout error will occur in any case.
26.6.19.3 Continue after System Bus Failure
If the SBFF bit in the Module Configuration Register (FR_MCR) is 0, the CC will continue its operation
after the occurrence of the system bus access failure but will not generate any system bus accesses until
the start of the next communication cycle.
If a frame is under transmission when the system bus failure occurs, a correct frame is generated with the
remaining header and frame data are replaced by all zeros. Depending on the point in time this can affect
the PPI bit, the Header CRC, the Payload Length in case of an dynamic slot, and the payload data. Starting
from the next slot in the current cycle, no frames will be transmitted and received, except for the key slot,
where a sync or startup null-frame is transmitted, if the key slot is assigned.
If a frame is received when the system bus failure occurs, the reception is aborted and the related receive
message buffer is not updated.
Normal operation is resumed after the start of next communication cycle.
26.6.19.4 Freeze after System Bus Failure
If the SBFF bit in the Module Configuration Register (FR_MCR) is set to 1, the CC will go into the freeze
mode immediately after the occurrence of one of the system bus access failures.
26.6.20 Interrupt Support
The CC provides 108 individual interrupt sources and five combined interrupt sources.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
26-163