PXS20RM Datasheet, PDF (46/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Introduction
• 3 cycles worst case for missed branch
• Load/store unit
— Fully pipelined
— Single-cycle load latency
— Big- and little-endian modes supported
— Misaligned access support
— Single stall cycle on load to use
• Single-cycle throughput (2-cycle latency) integer 32 × 32 multiplication
• 4 – 14 cycles integer 32 × 32 division (average division on various benchmark of nine cycles)
• Single precision floating-point unit
— 1 cycle throughput (2-cycle latency) floating-point 32 × 32 multiplication
— Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 × 32 division
— Special square root and min/max function implemented
• Signal processing support: APU-SPE 1.1
— Support for vectorized mode: as many as two floating-point instructions per clock
• Vectored interrupt support
• Reservation instruction to support read-modify-write constructs
• Extensive system development and tracing support via Nexus debug port
1.4.2 Crossbar Switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and
three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows four concurrent transactions to occur from any master port to any slave port, although
one of those transfers must be an instruction fetch from internal flash memory. If a slave port is
simultaneously requested by more than one master port, arbitration logic selects the higher priority master
and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the
higher priority master completes its transactions.
The crossbar provides the following features:
• 4 masters and 3 slaves supported per each replicated crossbar
— Masters allocation for each crossbar: e200z4d core with two independent bus interface units
(BIU) for I and D access (2 masters), one eDMA, one FlexRay
— Slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to
guarantee maximum flexibility to handle Instruction and Data array, one redundant SRAM
controller with 1 slave port each and 1 redundant peripheral bus bridge
• 32-bit address bus and 64-bit data bus
• Programmable arbitration priority
PXS20 Microcontroller Reference Manual, Rev. 1
1-6
Freescale Semiconductor