PXS20RM Datasheet, PDF (1163/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Peripheral Bridge (PBRIDGE)
0
R
0
1
2
3
SP
WP
TP
W
Reset
0
1
1
0
0
NOTES:
1 _{The reset state of PACR0[TP] is 1, not 0. PACR0[SP] and PACR0[TP] are hard wired to 1 and cannot}
be changed. Therefore, untrusted masters or user-mode accesses are always denied.
Figure 37-3. PACRn field structure
Table 37-5. PACRn field structure descriptions
Subfield
Description
SP
Supervisor Protect. This bit determines whether the peripheral requires supervisor privilege level for
access.
0 This peripheral does not require supervisor privilege level for accesses.
1 This peripheral requires supervisor privilege level for accesses. The MPROTx[MPL] control bit for
the master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
WP Write Protect. This bit determines whether the peripheral allows write accesses.
0 This peripheral allows write accesses.
1 This peripheral is write protected. If a write access is attempted, the access is terminated with an
error response and no peripheral access is initiated on the IPS bus.
TP
Trusted Protect. This bit determines whether the peripheral allows accesses from an untrusted master.
0 Accesses from an untrusted master are allowed.
1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted
master, the access is terminated with an error response and no peripheral access is initiated on the
IPS bus.
PBRIDGE
XBAR
MPU
SEMA4
SWT
STM
ECSM
eDMA
INTC
Table 37-6. On-platform peripherals and PACR numbers
Peripheral
PACR number
0
1
4
9
14
15
16
17
18
37.4.3.3 Off-platform peripheral access control registers (OPACR)
The OPACR defines the access levels supported by the associated module. Each OPACR has a format
identical to the PACR described in Section 37.4.3.2, Peripheral access control registers (PACR).
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
37-5