PXS20RM Datasheet, PDF (1028/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

LIN Controller (LINFlexD)
Offset: 0x94
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
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29
30
31
R0 0 0 0
CTO
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-40. UART current timeout register (UARTCTO)
Field
CTO
Table 31-38. UARTCTO field descriptions
Description
Current value of the timeout counter
This field is reset whenever one of the following occurs:
• A new value is written to the UARTPTO register
• The value of this field matches the value of UARTPTO[PTO]
• A hard or soft reset occurs
• New incoming data is received
When CTO matches the value of UARTPTO[PTO], UARTSR[TO] is set.
31.10.24 DMA Tx enable register (DMATXE)
This register enables the DMA Tx interface.
Offset: 0x98
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R DTE DTE DTE DTE DTE DTE DTE DTE DTE DTE DTE DTE DTE DTE DTE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-41. DMA Tx enable register (DMATXE)
31-52
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor