PXS20RM Datasheet, PDF (927/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
Table 28-3. Order of ISR execution example
Code executing at end of step
Step
#
Step Description
RTOS
ISR108¹ ISR208
ISR308
ISR408
interrupt
exception
handler
PRI in
INTC_CPR
at end of
step
1
RTOS at priority 0 is
X
0
executing.
2 Peripheral interrupt request
X
1
100 at priority 1 asserts.
Interrupt taken.
3 Peripheral interrupt request
400 at priority 4 is asserts.
Interrupt taken.
X
4
4 Peripheral interrupt request
300 at priority 3 is asserts.
X
4
5 Peripheral interrupt request
200 at priority 3 is asserts.
X
4
6 ISR408 completes. Interrupt
exception handler writes to
INTC_EOIR_PRC0.
X
1
7 Interrupt taken. ISR208 starts
X
3
to execute, even though
peripheral interrupt request
300 asserted first.
8 ISR208 completes. Interrupt
exception handler writes to
INTC_EOIR_PRC0.
X
1
9 Interrupt taken. ISR308 starts
to execute.
X
3
10 ISR308 completes. Interrupt
exception handler writes to
INTC_EOIR_PRC0.
X
1
11 ISR108 completes. Interrupt
exception handler writes to
INTC_EOIR_PRC0.
X
0
12 RTOS continues execution.
X
0
NOTES:
1 _{ISR108 executes for peripheral interrupt request 100 because the first eight ISRs are for software settable interrupt}
requests.
28.6.6 Priority Ceiling Protocol
28.6.6.1 Elevating Priority
The PRI field in Section 28.4.4, INTC Current Priority Register for Processor 0 (INTC_CPR_PRC0), is
elevated in the OSEK PCP to the ceiling of all of the priorities of the ISRs that share a resource. This
protocol therefore allows coherent accesses of the ISRs to that shared resource.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
28-21