PXS20RM Datasheet, PDF (193/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Analog-to-Digital Converter (ADC)
Field
AWDE
WDTE
THRH
THRL
Table 9-42. STAW4R field descriptions
Description
Analog watchdog enable
0 The analog watchdog related to the algorithm C is disabled
1 The analog watchdog related to the algorithm C is enabled
Watchdog timer enable. The watchdog timer verifies:
• Correct sequence of the algorithm (step sequence)
• Execution of the algorithm within the safe time period as defined by STBRR[WDT]
As soon as the watchdog timer is enabled the algorithm starting must be detected within the
safe time period. The watchdog timer is reset each time the algorithm restarts.
Note: This bit should be set only in scan mode.
0 The watchdog timer related to the algorithm C is disabled
1 The watchdog timer related to the algorithm C is enabled
High threshold value for channel n. If the analog watchdog is enabled, the STSR1[ERRn]
status bit is set if STDR1[TCDATA] > THRH.
Note: This value is valid only for the step 0 (refer to STAW5R register for the other Algorithm
C steps).
Low threshold value for channel n. If the analog watchdog is enabled, the STSR1[ERRn]
status bit is set if STDR1[TCDATA] < THRH.
Note: This value is valid only for the step 0 (refer to STAW5R register for the other Algorithm
C steps).
9.3.17.17 Self Test Analog Watchdog Register 5 (STAW5R)
Address: Base + 0x398
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0
W
THRH
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0
W
THRL
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Figure 9-41. Self Test Analog Watchdog Register 5 (STAW5R)
Table 9-43. STAW5R field descriptions
Field
THRH
THRL
Description
High threshold value (unsigned coding) for the algorithm C (step1 to step CS-1). If the analog
watchdog is enabled (STAW4R[AWDE] = 1), the STSR1[ERR_C] status bit is set if
STDR1[TCDATA{Stepn}] - STDR1[TCDATA {algC-step0}] > THRH.
Low threshold value (unsigned coding) for the algorithm C (step1 to step CS-1). If the analog
watchdog is enabled (STAW4R[AWDE] = 1), the STSR1[ERR_C] status bit is set if
STDR1[TCDATA {algC-step0}] - STDR1[TCDATA{Stepn}] > THRL.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
9-35