PXS20RM Datasheet, PDF (239/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Clock Monitor Unit (CMU)
Table 12-4. CMU_CSR field descriptions (continued)
RCDIV
CME_A
IRCOSC clock division factor
These bits specify the IRCOSC clock division factor. The output clock is IRCOSC_CLK divided by the
factor 2^RCDIV. This output clock is compared with XOSC_CLK for crystal clock monitor feature.The clock
division coding is as follows.
00 Clock divided by 1 (No division).
01 Clock divided by 2.
10 Clock divided by 4.
11 Clock divided by 8.
Clock monitor enable
0 Monitor is disabled.
1 Monitor is enabled.
12.3.2 Frequency display register (CMU_FDR)
Address: Base + 0x04
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0
FD[19:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
FD[15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-2. Frequency display Register (CMU_FDR)
Table 12-5. CMU_FDR field descriptions
Field
FD
Description
Measured frequency bits
This register displays the measured frequency f_{IRCOSC_CLK} with respect to f_{XOSC_CLK}. The measured
value is given by the following formula:
F_{IRCOSC_CLK} = (F_{XOSC_CLK} × MD) / n
where n is the value in CMU_FDR register
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
12-3