PXS20RM Datasheet, PDF (1043/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

LIN Controller (LINFlexD)
Table 31-48. TCD settings (UART node, TX mode) (continued)
TCD Field
SOFF[15:0]
SSIZE[2:0]
SLAST[31:0]
DADDR[31:0]
DOFF[15:0]
DSIZE[2:0]
DLAST_SGA[31:0]
INT_MAJ
D_REQ
START
Value
8-bit data
1
0
-M
BDRL address
16-bit data
2
1
-M * 2
0
0
1
0
0/1
1
0
Description
Byte/Half-word increment
Byte/Half-word transfer
DADDR = BDRL + 0x3 for byte transfer
DADDR = BDRL + 0x2 for half-word
transfer
No increment (FIFO)
Byte/Half-word transfer
No scatter/gather processing
Interrupt disabled/enabled
Only on the last TCD of the chain.
No software request
31.11.6 UART node, RX mode
In UART RX mode, the DMA interface requires a DMA RX channel. A single TCD can control the
reception of an entire Rx buffer. The memory map associated with the TCD chain (RAM area and
LINFlexD registers) is shown in Figure 31-53.
LINFlex2 registers
RAM area
DMA transfer (8/16-bits data format)
Buffer (n)
BDRM
(4 bytes FIFO mode)
BDRM
(2 half-words FIFO mode)
BDRM
(M bytes)
BDRM
(M half-words)
TCD (n)
Buffer (n+1)
BDRM
(4 bytes FIFO mode)
BDRM
(2 half-words FIFO mode)
BDRM
(M bytes)
BDRM
(M half-words)
TCD (n+1)
1 DMA RX channel (TCD single and/or linked chain)
Figure 31-53. TCD chain memory map (UART node, RX mode)
The UART RX buffer must be configured in FIFO mode in order to:
• Allow the transfer of large data buffer by a single TCD
• Adsorb the latency, following a DMA request (due to the DMA arbitration), to move data from the
FIFO to the RAM
• Use low priority DMA channels
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
31-67