PXS20RM Datasheet, PDF (1075/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Mode Entry Module (MC_ME)
32.3.2.5 Interrupt Mask Register (ME_IM)
Address 0xC3FD_C010
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 32-8. Interrupt Mask Register (ME_IM) for cut1
Address 0xC3FD_C010
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 32-9. Interrupt Mask Register (ME_IM) for cut2/3
This register controls whether an event generates an interrupt or not.
Table 32-8. Interrupt Mask Register (ME_IM) field descriptions
Field
M_CONF_CU
(cut2/3 only)
M_ICONF
M_IMODE
Description
Invalid mode configuration (clock usage) interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
Invalid mode configuration interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
Invalid mode interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
32-19