PXS20RM Datasheet, PDF (424/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x18
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
dlast_sga[0:15]
W
RESET: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
dlast_sga[16:31]
W
RESET: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
= Unimplemented
Figure 19-25. TCDn Word 6 (TCDn.dlast_sga) Field
Table 19-34. TCDn Word 6 (TCDn.dlast_sga) field description
Name
Description
Value
dlast_sga[31:0
0:31]
Last destination address adjustment or
the memory address for the next transfer
control descriptor to be loaded into this
channel (scatter/gather)
if (TCD.e_sg = 0) then
Adjustment value added to the destination address at
the completion of the outer major iteration count.
This value can be applied to “restore” the destination
address to the initial value, or adjust the address to
reference the next data structure.
else
This address points to the beginning of a 0-modulo-32
region containing the next transfer control descriptor to
be loaded into this channel. This channel reload is
performed as the major iteration count completes. The
scatter/gather address must be 0-modulo-32, else a
configuration error is reported.
Figure 19-26 and Table 19-35 define word 7 of the TCDn structure, the biter and control/status fields.
01
R biter.
W ^e_lin
k
RESET: -
-
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x1c
2 3 4 5 6 7 8 9 10 11 12 13 14 15
biter[0:5] or
biter[6:14]
biter.linkch[0:5]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
bwc
W
major.linkch[0:5]
done active major. e_sg d_req int_ha int_m start
e_link
lf
aj
RESET: -
-
-
-
-
-
-
-
0
0
-
-
-
-
-
0
= Unimplemented
Figure 19-26. TCDn Word 7 (TCDn.{biter,control/status}) Fields
19-28
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor