PXS20RM Datasheet, PDF (497/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
Field
PREMR
Table 21-20. PREMR field descriptions
Description
Platform RAM ECC Master Number
This 4-bit field contains the XBAR bus master number of the faulting access of the last,
correctly-enabled RAM ECC event.
21.4.2.19 Platform RAM ECC Attributes (PREAT) register
The PREAT is an 8-bit register for capturing the XBAR bus master attributes of the last, properly-enabled
ECC event in the platform RAM. Depending on the state of the ECC Configuration Register, an ECC event
in the platform RAM causes the address, attributes and data associated with the access to be loaded into
the PREAR, PRESR, PREMR, PREAT, PREDRL, and PREDRH registers, and the appropriate flag
(R1BC or RNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. If no
RAM ECC event is defined to be handled for this module, accesses to this register will terminate with an
error.
See Figure 21-19 and Table 21-21 for the PREAT definition.
Register address: ECSM Base + 0x0067
0
1
2
3
4
5
6
7
R
WRITE
SIZE
PROTECTION
W
RESET:
-
-
-
-
-
-
-
-
= Unimplemented
Figure 21-19. Platform RAM ECC Attributes (PREAT) Register
Table 21-21. PREAT field descriptions
Field
WRITE
SIZE
PROTECTION
Description
AMBA-AHB HWRITE
0 = AMBA-AHB read access
1 = AMBA-AHB write access
AMBA-AHB HSIZE[0:2]
0b000 = 8-bit AMBA-AHB access
0b001 = 16-bit AMBA-AHB access
0b010 = 32-bit AMBA-AHB access
0b1xx = Reserved
AMBA-AHB HPROT[0:3]
Protection[3]: Cacheable 0 = Non-cacheable, 1 = Cacheable
Protection[2]: Bufferable 0 = Non-bufferable,1 = Bufferable
Protection[1]: Mode 0 = User mode, 1 = Supervisor mode
Protection[0]: Type 0 = I-Fetch, 1 = Data
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
21-23