PXS20RM Datasheet, PDF (185/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

9.3.17.5 Self Test Status Register 1 (STSR1)
Address: Base + 0x350
0
1
2
3
4
5
6
7
8
R
Analog-to-Digital Converter (ADC)
Access: User read/write
9
10
11
12
13
14
15
0000
0
0000
W
w1c
w1c w1c w1c
w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
STEP_C
STEP_RC
W w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-29. Self Test Status Register 1 (STSR1)
Table 9-31. STSR1 field descriptions
Field
WDSERR
WDTERR
OVERWR
ST_EOC
WDG_EOA_C
WDG_EOA_RC
Description
Watchdog sequence error of the ADC sub-system (check for algorithm step sequence). It
generates an interrupt if enabled (STCR2[MSKWDSERR] = 1). It provides the fault indication
to the FCCU, asserting CF or NCF according to the STCR2[FMA_WDSERR] mapping.
0 no failure
1 failure occurred
Watchdog timer error of the ADC sub-system (algorithm check for completion within safe
time). It generates an interrupt if enabled (STCR2[MSKWDTERR] = 1). It provides the fault
indication to the FCCU, asserting CF or NCF according to the STCR2[FMA_WDTERR]
mapping.
0 no failure
1 failure occurred
Overwrite error. Used to notify when the STSR1[ERRn] bit is overwritten by a newer one. The
new error status is written or discarded according to the MCR[OWREN] bit value. To avoid
OVERWR indication, the ERRn status bit must be cleared (via SW).
Self Test EOC Bit. If IMR[MSKEOC] = 1, this bit is set along with EOC bit when
end_of_conversion signal is received from ADC analog for self test channel. It generates an
interrupt if enabled by STCR2[MSKST_EOC].
This bit indicates that Algorithm C has been completed. This bit is set after the last step of the
algorithm is executed. It generates an interrupt if enabled (STCR2[MSKWDG_EOA_C] = 1).
This bit is set only if STAW4R[WDTE] = 1.
For CTU conversions, this bit is significant only for Burst mode of operation.
This bit indicates that Algorithm RC has been completed. This bit is set after the last step of
the algorithm is executed. It generates an interrupt if enabled
(STCR2[MSKWDG_EOA_RC] = 1). This bit is set only if STAW3R[WDTE] = 1.
For CTU conversions, this bit is significant only for Burst mode of operation.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
9-27