PXS20RM Datasheet, PDF (462/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Motor Control Timer (eTimer)
If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled
capture circuit.
ARM - Arm Capture
Setting this bit high starts the input capture process. This bit can be cleared at any time to disable input
capture operation. This bit is self cleared when in one shot mode and the enabled capture circuit(s) has
had a capture event(s).
1 = Input capture operation as specified by the CPT1MODE and CPT2MODE bits is enabled.
0 = Input capture operation is disabled.
20.4.3.16 Input Filter Register (FILT)
eTimer_CHNL ₀
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
_BASE + $1E
Read
Write
0000 0
FILT_CNT[2:0]
FILT_PER[7:0]
Reset
0000 0 00000000000
Figure 20-18. Input Filter Register (FILT)
FILT_CNT - Input Filter Sample Count
These bits represent the number of consecutive samples that must agree prior to the input filter
accepting an input transition. A value of 0 represents 3 samples. A value of 7 represents 10 samples.
The value of FILT_CNT affects the input latency as described in Section 20.4.3.16.1, Input Filter
Considerations.
FILT_PER - Input Filter Sample Period
These bits represent the sampling period (in IPBus clock cycles) of the eTimer input signal. Each input
is sampled multiple times at the rate specified by FILT_PER. If FILT_PER is $00 (default), then the
input filter is bypassed. The value of FILT_PER affects the input latency as described in
Section 20.4.3.16.1, Input Filter Considerations.
20.4.3.16.1 Input Filter Considerations
The FILT_PER value should be set such that the sampling period is larger the period of the expected noise.
This way a noise spike will only corrupt one sample. The FILT_CNT value should be chosen to reduce
the probability of noisy samples causing an incorrect transition to be recognized. The probability of an
incorrect transition is defined as the probability of an incorrect sample raised to the FILT_CNT + 3 power.
The values of FILT_PER and FILT_CNT must also be traded off against the desire for minimal latency in
recognizing input transitions. Turning on the input filter (setting FILT_PER to a non-zero value)
introduces a latency of: (((FILT_CNT + 3) x FILT_PER) + 2) IPBus clock periods.
20.4.4 Watchdog Timer Registers
The base address of the Watchdog Timer registers is equal to the base address of the eTimer plus an offset
of $100.
20-20
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor