PXS20RM Datasheet, PDF (432/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
eDMA
eDMA engine
hrdata[63:0]
data_path
SRAM
Transfer
Control
Descriptor (TCD)
pmodel_charb
addr_path
c
o
n
t
r
o
l
addr
wdata[31:0]
0
j
j+1
n-1
rdata[31:0]
Peripheral
Bus
AMBA
Bus
hwdata[63:0]
haddr[31:0]
dma_ipi_int[n-1:0]
dma_ipd_done[n-1:0]
ipd_req[n-1:0]
Figure 19-29. eDMA operation, part 3
19.3.3 eDMA performance
This section addresses the performance of the eDMA module, focusing on two separate metrics. In the
traditional data movement context, performance is best expressed as the peak data transfer rates achieved
using the eDMA. In most implementations, this transfer rate is limited by the speed of the source and
destination address spaces. In a second context where device-paced movement of single data values
to/from peripherals is dominant, a measure of the requests which can be serviced in a fixed time is a more
interesting metric. In this environment, the speed of the source and destination address spaces remains
important, but the microarchitecture of the eDMA also factors significantly into the resulting metric.
The peak transfer rates for several different source and destination transfers are shown in Table 19-36. The
following assumptions apply to Table 19-36 and Table 19-37:
• Platform SRAM can be accessed with zero wait-states when viewed from the AMBA-AHB data
phase
• All IPS reads require two wait-states, and IPS writes three wait-states, again viewed from the
system bus data phase
• All IPS accesses are 32 bits in size
19-36
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor