PXS20RM Datasheet, PDF (876/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
26.6.20.1 Individual Interrupt Sources
26.6.20.1.1 Message Buffer Interrupts
The CC provides 64 message buffer interrupt sources.
Each individual message buffer provides an interrupt flag FR_MBCCSRn[MBIF] and an interrupt enable
bit FR_MBCCSRn[MBIE]. The CC sets the interrupt flag when the slot status of the message buffer was
updated. If the interrupt enable bit is asserted, an interrupt request is generated.
26.6.20.1.2 FIFO Interrupts
The CC provides 2 FIFO interrupt sources.
Each of the 2 FIFO provides a Receive FIFO Almost Full Interrupt Flag. The CC sets the Receive FIFO
Almost Full Interrupt Flags (FR_GIFER[FAFBIF], FR_GIFER[FAFAIF]) in the Global Interrupt Flag and
Enable Register (FR_GIFER) if the corresponding Receive FIFO fill level exceeds the defined watermark.
26.6.20.1.3 Wakeup Interrupt
The CC provides one interrupt source related to the wakeup.
The CC sets the Wakeup Interrupt Flag FR_GIFER[WUPIF] when it has received a wakeup symbol on the
FlexRay bus. The CC generates an interrupt request if the interrupt enable bit FR_GIFER[WUPIE] is
asserted.
26.6.20.1.4 Protocol Interrupts
The CC provides 25 interrupt sources for protocol related events. For details, see Protocol Interrupt Flag
Register 0 (FR_PIFR0) and Protocol Interrupt Flag Register 1 (FR_PIFR1). Each interrupt source has its
own interrupt enable bit.
26.6.20.1.5 CHI Interrupts
The CC provides 16 interrupt sources for CHI related error events. For details, see CHI Error Flag Register
(FR_CHIERFR). There is one common interrupt enable bit FR_GIFER[CHIE] for all CHI error interrupt
sources.
26.6.20.2 Combined Interrupt Sources
Each combined interrupt source generates an interrupt request only when at least one of the interrupt
sources that is combined generates an interrupt request.
26.6.20.2.1 Receive Message Buffer Interrupt
The Receive Message Buffer Interrupt request is generated when at least one of the individual receive
message buffers generates an interrupt request MBXIRQ[n] and the interrupt enable bit FR_GIFER[RBIE]
is set.
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PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor