PXS20RM Datasheet, PDF (594/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
Table 23-26. PFLASH Configuration Register 0 (PFCR0) settings for different frequencies
Frequency
<=120MHz
<=80MHz
<=60MHz
Flash Wait State
3
2
1
APC field
3
2
1
WWSC field
3
2
1
RWSC field
3
2
1
RAM Wait State
0
0
0
NOTE
The fields APC, WWSC and RWSC of the PFLASH Configuration Register
0 (PFCR0) should be set to the same value.
The RAM WS are configured by the MUDCR bit in the Miscellaneous
User-Defined Control Register (MUDCR).
23.2.2.2 Platform Flash Access Protection Register (PFAPR)
The PFLASH Access Protection Register (PFAPR) is used to control read and write accesses to the flash
based on system master number. Prefetching capabilities are defined on a per master basis. This register
also defines the arbitration mode between the 2 AHB ports for the PFLASH2P_LCA. The register is
described below in Figure 23-26 and Table 23-27.
The contents of the register are loaded from location 0x203E00 of the shadow region in the flash memory
array at reset. To temporarily change the values of any of the fields in the PFAPR, a write to the
IPS-mapped register is performed. To change the values loaded into the PFAPR at reset, the word location
at address 0x203E00 of the shadow region in the flash array must be programmed using the normal
sequence of operations. The reset value shown in Figure 23-26 reflects an erased or unprogrammed value
from the shadow region.
Offset 0x024
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0 0 0
W
ARBM
M7P M6P M5P M4P M3P M2P M1P M0P
FD FD FD FD FD FD FD FD
Reset * * * * * * 1 1 1 1 1 1 1 1 1 1
16 17
R
M7AP
W
18 19
M6AP
20 21
M5AP
22 23
M4AP
24 25
M3AP
26 27
M2AP
28 29
M1AP
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 23-26. PFLASH Access Protection Register (PFAPR)
30 31
M0AP
11
23-44
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor