PXS20RM Datasheet, PDF (333/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Address: DSPI_BASE + 0xC
0
1
2
3
4
5
R
W
SLAVE_FMSZ
Deserial Serial Peripheral Interface (DSPI)
Access:
6
7
8
9
10
11
12
13
14
15
0000000
Reset 0 1 1 1 1
0
0
000000000
16
17
18
19
20
21
R0 0 0 0 0
0
22
23
24
25
26
27
28
29
30
31
0
0
000
00
0
00
W
Reset 0 0 0 0 0
0
0
000000000
Figure 16-9. DSPI Clock and Transfer Attributes Register 0 (DSPI_CTAR0) in slave mode for cut2/3
Table 16-6. DSPI_CTARn field descriptions in master mode
Field
DBR
FMSZ
CPOL
CPHA
LSBFE
Descriptions
Double Baud Rate. The DBR bit doubles the effective baud rate of the Serial Communications Clock
(SCK). This field is only used in master mode. It effectively halves the Baud Rate division ratio
supporting faster frequencies and odd division ratios for the Serial Communications Clock (SCK).
When the DBR bit is set, the duty cycle of the Serial Communications Clock (SCK) depends on the
value in the Baud Rate Prescaler and the Clock Phase bit as listed in Table 16-7. See the BR field
description for details on how to calculate the baud rate.
If the overall baud rate is divide by two or divide by three of the system clock then neither the
Continuous SCK Enable or the Modified Timing Format Enable bits should be set.
0 The baud rate is computed normally with a 50/50 duty cycle
1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler
Frame Size. The number of bits transferred per frame is equal FMSZ field value plus 1. Minimum valid
FMSZ field value is 3.
Clock Polarity. The CPOL bit selects the inactive state of the Serial Communications Clock (SCK).
This bit is used in both master and slave mode. For successful communication between serial
devices, the devices must have identical clock polarities. When the Continuous selection format is
selected, switching between clock polarities without stopping the DSPI can cause errors in the
transfer due to the peripheral device interpreting the switch of clock polarity as a valid clock edge.
0 The inactive state value of SCK is low
1 The inactive state value of SCK is high
Clock Phase. The CPHA bit selects which edge of SCK causes data to change and which edge
causes data to be captured. This bit is used in both master and slave mode. For successful
communication between serial devices, the devices must have identical clock phase settings. In
Continuous SCK mode the bit value is ignored and the transfers are done as CPHA bit is set to 1.
0 Data is captured on the leading edge of SCK and changed on the following edge
1 Data is changed on the leading edge of SCK and captured on the following edge
LSB First. The LSBFE bit selects if the LSB or MSB of the frame is transferred first.
0 Data is transferred MSB first
1 Data is transferred LSB first
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
16-13