PXS20RM Datasheet, PDF (911/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Interrupt Controller (INTC)
Table 28-1. INTC memory map (continued)
Offset from
INTC_BASE
Register
Access¹ Reset value²
Location
0x0024
INTC Software Set/Clear Interrupt Register 4 - 7
(INTC_SSCIR4_7)
R/W 0x0000_0000 on page 28-9
0x0028–0x003C Reserved
0x0040–0x013C INTC Priority Select Register 0 - 3 (INTC_PSR0_3) - R/W
INTC Priority Select Register 252 - 255
(INTC_PSR252_255)³
0x0000_0000 on page 28-11
0x0140–0x3FFF Reserved
NOTES:
1 _{In this column, R/W = Read/Write, R = Read-only, and W = Write-only.}
2 _{In this column, the symbol “U” indicates one or more bits in a byte are undefined at reset. See the associated}
description for more information.
3 _{The PRI fields are 'reserved' for peripheral interrupt requests whose vectors are labeled as Not Used in Table 28-4.}
28.4.2 Register Information
With exception of the INTC_SSCIRn and INTC_PSRn, all registers are 32 bits in width. Any combination
of accessing the four bytes of a register with a single access is supported, provided that the access does not
cross a register boundary. These supported accesses include types and sizes of 8 bits, aligned 16 bits,
misaligned 16 bits to the middle 2 bytes, and aligned 32 bits.
Although INTC_SSCIRn and INTC_PSRn are 8 bits wide, they can be accessed with a single 16-bit or
32-bit access, provided that the access does not cross a 32-bit boundary.
In software vector mode, the side effects of a read of INTC_IACKR_PRC0 are the same regardless of the
size of the read. In either software or hardware vector mode, the size of a write to INTC_SSCIRn or
INTC_EOIR_PRC0 does not affect on the operation of the write.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
28-5