PXS20RM Datasheet, PDF (1283/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Chapter 43
Semaphore Unit (SEMA4)
Semaphore Unit (SEMA4)
43.1 Introduction
PXS20 contains two SEMA4 units.
In a dual-processor chip, semaphores are used to let each processor know who has control of common
memory. Before a core can update or read memory coherently, it has to check the semaphore to see if the
other core is not already updating the memory. If the semaphore is clear, it can write common memory, but
if it is set, it has to wait for the other core to finish and clear the semaphore.
The semaphore unit (SEMA4) provides the hardware support needed in multi-core systems for
implementing semaphores and provide a simple mechanism to achieve lock/unlock operations via a single
write access. This approach eliminates architecture-specific implementations like atomic (indivisible)
read-modify-write instructions or reservation mechanisms. The result is an architecture-neutral solution
that provides hardware-enforced gates as well as other useful system functions related to the gating
mechanisms.
On PXS20, the SEMA4 unit is intended for use when using the device in dual processor mode. When using
the device in Lock Step mode, the SEMA4 unit is disabled and its interrupt sources deasserted.
In this chapter, the two instantiations of the e200z4d core on PXS20 are referred to as e200z4d_0 and
e200z4d_1. (The e200z4d_0 instantiation runs from reset in dual processor mode.)
43.1.1 Block diagram
Figure 43-1 is a simplified block diagram of the SEMA4 unit that illustrates the functionality and
interdependence of major blocks. In the diagram, the register blocks named gate0, gate1, ..., gate 15
include the finite state machines implementing the semaphore gates plus the interrupt notification logic.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
43-1