PXS20RM Datasheet, PDF (1275/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Self-Test Control Unit (STCU)
Field
MISREL
Table 42-13. STCU_LB_MISREL field descriptions
Description
MISR Expected low part
MISREL defines the low part of the Expected MISR.
42.4.3.12 STCU LBIST MISR Expected High Register (STCU_LB_MISREH) [cut2/3
only]
The STCU_LB_MISREH register defines the MSB part of the Expected MISR of each LBIST controller.
Address: Base + 0x008C + (n × 0x20)¹ [cut2/3 only]
Access: User read
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
MISREH[31:16]
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
MISREH[15:0]
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 42-17. STCU LBIST MISR Expected High Register (STCU_LB_MISREH) [cut2/3 only]
NOTES:
1 _{The n variable represents the repeated register blocks of the multiple LBISTs: n ranges from 0 up to 2.}
Field
MISREH
Table 42-14. STCU_LB_MISREH field descriptions
Description
MISR Expected high part
MISREH defines the high part of the Expected MISR.
42.4.3.13 STCU LBIST MISR Read Low Register (STCU_LB_MISRRL)
The STCU_LB_MISRRL registers report the LSB part of the MISR obtained at the end of each LBIST.
Address: Base + 0x0090 + (n × 0x20)¹
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R
MISRRL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
MISRRL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 42-18. STCU LBIST MISR Read Low Register (STCU_LB_MISRRL)
NOTES:
1 _{The n variable represents the repeated register blocks of the multiple LBISTs: n ranges from 0 up to 2.}
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
42-17