PXS20RM Datasheet, PDF (796/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
Table 26-80. FR_EEIFER Field Descriptions (continued)
Field
LRNE_IF
LRCE_IF
DRNE_IF
DRCE_IF
LRNE_IE
LRCE_IE
DRNE_IE
DRCE_IE
Description
Error Interrupt Flags
LRAM Non-Corrected Error Interrupt Flag — This interrupt flag is set to 1 when a memory error
is detected but not corrected on the CHI LRAM.
0 no such event
1 Non-Corrected Error detected on CHI LRAM
LRAM Corrected Error Interrupt Flag — This interrupt flag is set to 1 when a memory error is
detected and corrected on the CHI LRAM.
0 no such event
1 Corrected Error detected on CHI LRAM
Note: Error Correction not implemented on CHI LRAM, flag will never be asserted.
DRAM Non-Corrected Error Interrupt Flag — This interrupt flag is set to 1 when a memory error
is detected but not corrected on PE DRAM.
0 no such event
1 Non-Corrected Error detected on PE DRAM
DRAM Corrected Error Interrupt Flag — This interrupt flag is set to 1 when a memory error is
detected and corrected on PE DRAM.
0 no such event
1 Corrected Error detected on PE DRAM
Error Interrupt Enables
LRAM Non-Corrected Error Interrupt Enable — This flag controls if the LRAM Non-Corrected
Error Interrupt line is asserted when the LRNE_IF flag is set.
0 Disable interrupt line
1 Enable interrupt line
LRAM Corrected Error Interrupt Enable — This flag controls if the LRAM Corrected Error
Interrupt line is asserted when the LRCE_IF flag is set.
0 Disable interrupt line
1 Enable interrupt line
DRAM Non-Corrected Error Interrupt Enable — This flag controls if the DRAM Non-Corrected
Error Interrupt line is asserted when the DRNE_IF flag is set.
0 Disable interrupt line
1 Enable interrupt line
DRAM Corrected Error Interrupt Enable — This flag controls if the DRAM Corrected Error
Interrupt line is asserted when the DRCE_IF flag is set.
0 Disable interrupt line
1 Enable interrupt line
26-84
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor