PXS20RM Datasheet, PDF (406/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Direct Memory Access (eDMA)
Register address: DMA_Offset + 0x000C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0000000000000000
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ
W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Name
ERQn,
n = 0,... 15
= Unimplemented
Figure 19-4. eDMA Enable Request Low (DMAERQL) Register
Table 19-4. DMAERQL field descriptions
Description
Enable eDMA Request n
Value
0 The eDMA request signal for channel n is disabled.
1 The eDMA request signal for channel n is enabled.
As a given channel completes the processing of its major iteration count, there is a flag in the transfer
control descriptor that may affect the ending state of the DMAERQ bit for that channel. If the TCD.d_req
bit is set, then the corresponding DMAERQ bit is cleared, disabling the eDMA request; else if the d_req
bit is cleared, the state of the DMAERQ bit is unaffected.
19.2.1.4 eDMA Enable Error Interrupt Low (DMAEEIL)
The DMAEEIL register provides a bit map for the implemented channels to enable the error interrupt
signal for each channel. The state of any given channel’s error interrupt enable is directly affected by writes
to this register; it is also affected by writes to the DMASEEI and DMACEEI registers. The
eDMA{S,C}EEI registers are provided so that the error interrupt enable for a single channel can easily be
modified without the need to perform a read-modify-write sequence to the DMAEEIL register.
Both the eDMA error indicator and this error interrupt enable flag must be asserted before an error
interrupt request for a given channel is asserted.
See Figure 19-5 and Table 19-5 for the DMAEEIL definition.
19-10
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor