PXS20RM Datasheet, PDF (848/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

FlexRay Communication Controller
State
Idle
Idle
CCMa
Table 26-121. Double Transmit Message Buffer Transition Priorities
Priority
IS > HD
IS > HL
MA > SA
TX > STS
TX > DSS
Description
module vs. application
Internal Message Transfer Start > Message Buffer Disable
Internal Message Transfer Start > Message Buffer Lock
module internal
Message Available > Slot Assigned
Transmission Slot Start > Static Slot Start
Transmission Slot Start > Dynamic Slot Start
26.6.6.4.4 Message Preparation
The application provides the message data through the commit side. The transmission itself is executed
from the transmit side. The transfer of the message data from the commit side to the transmit side is done
by the Internal Message Transfer, which is described in Section 26.6.6.4.5, Internal Message Transfer
To transmit a message over the FlexRay bus, the application writes the message data into the message
buffer data field of the commit side and sets the commit bit CMT in the Message Buffer Configuration,
Control, Status Registers (FR_MBCCSRn). The physical access to the message buffer data field is
described in Section 26.6.3.1, Individual Message Buffers.
As indicated by Table 26-117, the application shall write to the message buffer data field and change the
commit bit CMT only if the transmit message buffer is in one of the states HDis, HDisLck, or HLck. The
application can change the state of a message buffer if it issues the appropriate commands shown in
Table 26-119. The state change is indicated through the FR_MBCCSRn[EDS] and
FR_MBCCSRn[LCKS] status bits.
26.6.6.4.5 Internal Message Transfer
The internal message transfer transfers the message data from the commit side to the transmit side. The
internal message transfer is implemented as the swapping of the content of the Message Buffer Index
Registers (FR_MBIDXRn) of the commit side and the transmit side. After the swapping, the commit side
CMT bit is cleared, the commit side interrupt flag MBIF is set, the transmit side CMT bit is set, and the
transmit side DVAL bit is cleared.
The conditions and the point in time when the internal message transfer is started are controlled by the
message buffer commit mode bit MCM in the Message Buffer Configuration, Control, Status Registers
(FR_MBCCSRn). The MCM bit configures the message buffer for either the streaming commit mode or
the immediate commit mode. A detailed description is given in Streaming Commit Mode and Immediate
Commit Mode. The Internal Message Transfer is triggered with the transition IS. Both sides of the message
buffer enter one of the CCITx states. The internal message transfer is finished with the transition IE.
Streaming Commit Mode
The intention of the streaming commit mode is to ensure that each committed message is transmitted at
least once. The CC will not start the Internal Message Transfer for a message buffer as long as the message
data on the transmit side is not transmitted at least once.
26-136
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor