PXS20RM Datasheet, PDF (1132/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Nexus Port Controller (NPC)
Bit
31:28
27:22
21:12
11:1
0
Name
PRN
DC
PIN
MIC
Bit [0]
Table 34-4. DID Field Descriptions
Description
Part Revision Number
These bits contain the revision number of the part
Design Center
These bits indicate the device design center
Part Identification Number
These bits contain the part number of the device
Manufacturer Identity Code
These bits contain the reduced Joint Electron Device Engineering Council (JEDEC) ID for
Freescale Semiconductor, 0xE.
IDCODE Register ID
Bit [0] identifies this register as the device identification register and not the bypass register
34.4.1.4 Port Configuration Register (PCR)
Register index: 127
0123456789
R
FPM MCK MCK
MCKO_DIV
EVT_ DDR_ 0
0
W
O_GT O_EN
EN EN
RESET: 0 0 0 0 0 0 0 0 0 0
10 11 12 13 14 15
0
0
0
0
0
0
000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R LP_D 0
0
0
0
0 LP2_ LP1_ 0
0
0
0
0
0
0 PSTA
W
BG
SYN SYN
T_EN
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Reserved
Figure 34-4. Port Configuration Register (PCR)
The PCR, shown in Figure 34-4, is used to select the NPC mode of operation, enable MCKO and select
the MCKO frequency, and enable or disable MCKO gating. This register should be configured as soon as
the NPC is enabled.
The PCR register may be rewritten by the debug tool subsequent to the enabling of the NPC for low power
debug support. In this case, the debug tool may set and clear the LP_DBG and LPn_SYN bits, but must
preserve the original state of the remaining bits in the register.
NOTE
The mode or clock division must not be modified after MCKO has been
enabled. Changing the mode or clock division while MCKO is enabled can
produce unpredictable results.
34-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor