PXS20RM Datasheet, PDF (691/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flexible Motor Control Pulse Width Modulator Module (FlexPWM)
25.4.3.11 Output Control Register (OCTRL)
PWM_SUB
_BASE+$1 0 1 2 3 4 5 6 7 8 9 10 11
8
Read
Write
PWM PWM PWM
A_IN B_IN X_IN
0
0 _{POL POL POL} 0
ABX
0
PWMAFS
Reset
UUU0 0 0 0 0 0 0 0 0
Figure 25-45. Output Control Register (OCTRL)
12 13
PWMBFS
00
14 15
PWMXFS
00
PWMA_IN - PWMA Input
This read only bit shows the logic value currently being driven into the PWMA input.
PWMB_IN - PWMB Input
This read only bit shows the logic value currently being driven into the PWMB input.
PWMX_IN - PWMX Input
This read only bit shows the logic value currently being driven into the PWMX input.
POLA - PWMA Output Polarity
This bit inverts the PWMA output polarity.
1 = PWMA output inverted. A low level on the PWMA pin represents the "on" or "active" state.
0 = PWMA output not inverted. A high level on the PWMA pin represents the "on" or "active"
state.
POLB - PWMB Output Polarity
This bit inverts the PWMB output polarity.
1 = PWMB output inverted. A low level on the PWMB pin represents the "on" or "active" state.
0 = PWMB output not inverted. A high level on the PWMB pin represents the "on" or "active" state.
POLX - PWMX Output Polarity
This bit inverts the PWMX output polarity.
1 = PWMX output inverted. A low level on the PWMX pin represents the "on" or "active" state.
0 = PWMX output not inverted. A high level on the PWMX pin represents the "on" or "active"
state.
PWMAFS - PWMA Fault State
These bits determine the fault state for the PWMA output during fault conditions and STOP mode. It
may also define the output state during WAIT and DEBUG modes depending on the settings of
WAITEN and DBGEN.
• 00 = Output is forced to logic 0 state prior to consideration of output polarity control.
• 01 = Output is forced to logic 1 state prior to consideration of output polarity control.
• 1x = Output is tristated.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
25-45