PXS20RM Datasheet, PDF (469/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Motor Control Timer (eTimer)
20.5.2.9 CASCADE-COUNT Mode
If the CNTMODE field is set to ‘111’, the counter’s input is connected to the output of another selected
counter. The counter will count up and down as compare events occur in the selected source counter. This
“Cascade” or “Daisy-Chained” mode enables multiple counters to be cascaded to yield longer counter
lengths. When operating in cascade mode, a special high speed signal path is used between modules rather
than the OFLAG output signal. If the selected source counter is counting up and it experiences a compare
event, the counter will be incremented. If the selected source counter is counting down and it experiences
a compare event, the counter will be decremented.
Up to two counters may be cascaded to create a 32 bit wide synchronous counter.
Whenever any counter is read within a counter module, all of the counters’ values within the module are
captured in their respective HOLD registers. This action supports the reading of a cascaded counter chain.
First read any counter of a cascaded counter chain, then read the HOLD registers of the other counters in
the chain. The cascaded counter mode is synchronous.
NOTE
It is possible to connect counters together by using the other (non-cascade)
counter modes and selecting the outputs of other counters as a clock source.
In this case, the counters are operating in a “ripple” mode, where higher
order counters will transition a clock later than a purely synchronous design.
NOTE
A channel can be cascaded with any other channel, but you can’t cascade
more than 2 channels together. You can create separate cascades of pairs of
channels. For example, you can cascade channels 0 and 1 and separately
cascade channels 6 and 5. You can’t cascade channels 0, 1, and 5.
20.5.2.10 PULSE-OUTPUT Mode
If the counter is setup for CNTMODE = 001, and the OFLAG OUTMODE is set to ‘1111’ (gated clock
output), and the ONCE bit is set, then the counter will output a pulse stream of pulses that has the same
frequency of the selected clock source, and the number of output pulses is equal to the compare value
minus the init value. This mode is useful for driving step motor systems.
NOTE
This does not work if the PRISRC is set to 11000 (IP_bus/1).
CNTMODE
0
1
Primary
CNTR
0
1
2
3
4
0
OFLAG
Pulse Stream Init
LOAD = 0, COMP1 = 4
Figure 20-27. Pulse Output Mode
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
20-27