PXS20RM Datasheet, PDF (222/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Clock Generation Module (MC_CGM)
11.3.1.1 Output Clock Enable Register (CGM_OC_EN)
Address 0xC3FE_0370
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 11-2. Output Clock Enable Register (CGM_OC_EN)
This register is used to enable and disable the output clock.
Table 11-3. Output Clock Enable Register (CGM_OC_EN) Field Descriptions
Field
EN Output Clock Enable control
0 Output Clock is disabled
1 Output Clock is enabled
Description
11.3.1.2 Output Clock Division Select Register (CGM_OCDS_SC)
Address 0xC3FE_0374
Access: User read-only, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
R
0
0
W
SELDIV
SELCTL
Reset
0
0
0
0
0
0
0
0
Figure 11-3. Output Clock Division Select Register (CGM_OCDS_SC)
This register is used to select the current output clock source and by which factor it is divided before being
delivered at the output clock.
11-8
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor