PXS20RM Datasheet, PDF (909/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

28.2 Modes of Operation
Interrupt Controller (INTC)
28.2.1 Normal Mode
In normal mode, the INTC has two handshaking modes with the processor: software vector mode and
hardware vector mode.
28.2.1.1 Software Vector Mode
In software vector mode, software, that is the interrupt exception handler, must read a register in the INTC
to obtain the vector associated with the interrupt request to the processor. The INTC will use software
vector mode for a given processor when its associated INTC_BCR[HVEN_PRC0] bit is cleared. The
hardware vector enable signal to the processor is driven as negated when its associated HVEN_PRC0 bit
is negated. The vector is read from the INTC_IACKR_PRC0 register. Reading the INTC_IACKR_PRC0
negates the interrupt request to the associated processor. Even if a higher priority interrupt request arrived
while waiting for this interrupt acknowledge, the interrupt request to the processor will negate for at least
one clock. The reading also pushes the PRI value in the INTC_CPR register onto the associated LIFO and
updates PRI in the associated INTC_CPR_PRC0 with the new priority.
Furthermore, the interrupt vector to the processor is driven as all ‘0’s. The interrupt acknowledge signal
from the associated processor is ignored.
28.2.1.2 Hardware Vector Mode
In hardware vector mode, the hardware is the interrupt vector signal from the INTC in conjunction with a
processor with the capability to use that vector. In hardware vector mode, this hardware causes the first
instruction to be executed in handling the interrupt request to the processor to be specific to that vector.
Therefore the interrupt exception handler is specific to a peripheral or software settable interrupt request
rather than being common to all of them. The INTC will use hardware vector mode for a given processor
when its associated HVEN_PRC0 bit in the INTC_BCR is asserted. The hardware vector enable signal to
the associated processor is driven as asserted. When the interrupt request to the associated processor
asserts, the interrupt vector signal is updated. The value of that interrupt vector is the unique vector
associated with the preempting peripheral or software settable interrupt request. The vector value matches
the value of the INTVEC_PRC0 field in the INTC_IACKR_PRC0.
The processor negates the interrupt request to the processor driven by the INTC by asserting the interrupt
acknowledge signal for one clock. Even if a higher priority interrupt request arrived while waiting for this
interrupt acknowledge, the interrupt request to the processor will negate for at least one clock.
The assertion of the interrupt acknowledge signal for a given processor pushes the associated PRI value in
the associated INTC_CPR_PRC0 register onto the associated LIFO and updates the associated PRI in the
associated INTC_CPR_PRC0 register with the new priority. This pushing of the PRI value onto the
associated LIFO and updating PRI in the associated INTC_CPR_PRC0 does not occur when the associated
interrupt acknowledge signal asserts and the INTC_SSCIR register is written at a time such that the PRI
value in the associated INTC_CPR_PRC0 register would need to be pushed and the previously last pushed
PRI value would need to be popped simultaneously. In this case, PRI in the associated INTC_CPR_PRC0
is updated with the new priority, and the associated LIFO is neither pushed or popped.
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
28-3