PXS20RM Datasheet, PDF (490/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Error Correction Status Module (ECSM)
21.4.2.13 Platform Flash ECC Master Number Register (PFEMR)
The PFEMR is a 4-bit register for capturing the XBAR bus master number of the last, properly-enabled
ECC event in the platform flash memory. Depending on the state of the ECC Configuration Register, an
ECC event in the platform flash memory causes the address, attributes and data associated with the access
to be loaded into the PFEAR, PFEMR, PFEAT, PFEDRL, and PFEDRH registers, and the appropriate flag
(PF1BC or PFNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. If no flash
memory ECC event is defined to be handled for this module, accesses to this register will terminate with
an error.
See Figure 21-12 and Table 21-14 for the PFEMR definition.
Register address: ECSM Base + 0x0056
0
1
2
3
4
5
6
7
R
0
0
0
0
PFEMR
W
RESET:
0
0
0
0
-
-
-
-
= Unimplemented
Figure 21-12. Platform Flash Memory ECC Master Number (PFEMR) Register
Field
PFEMR
Table 21-14. PFEMR field descriptions
Description
Platform Flash Memory ECC Master Number
This 4-bit field contains the XBAR bus master number of the faulting access of the last,
properly-enabled platform flash memory ECC event.
21.4.2.14 Platform Flash Memory ECC Attributes (PFEAT) register
The PFEAT is an 8-bit register for capturing the XBAR bus master attributes of the last, properly-enabled
ECC event in the platform flash memory. Depending on the state of the ECC Configuration Register, an
ECC event in the platform flash memory causes the address, attributes and data associated with the access
to be loaded into the PFEAR, PFEMR, PFEAT, PFEDRL, and PFEDRH registers, and the appropriate flag
(F1BC or FNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. If no flash
memory ECC event is defined to be handled for this module, accesses to this register will terminate with
an error.
See Figure 21-13 and Table 21-15 for the PFEAT definition.
21-16
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor