PXS20RM Datasheet, PDF (456/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Enhanced Motor Control Timer (eTimer)
This bit allows the tri-stating of the timer output during stop mode.
1 = Output enable is disabled during stop mode.
0 = Output enable is unaffected by stop mode.
ROC - Reload on Capture
These bits enable the capture function to cause the counter to be reloaded from the LOAD register.
Table 20-8. Values for Reload on Capture
Value
Meaning
00
Do not reload the counter on a capture event.
01
Reload the counter on a capture 1 event.
10
Reload the counter on a capture 2 event.
11
Reload the counter on both a capture 1 event and a capture 2 event.
C2FCNT - CAPT2 FIFO Word Count
This field reflects the number of words in the CAPT2 FIFO.
C1FCNT - CAPT1 FIFO Word Count
This field reflects the number of words in the CAPT1 FIFO.
DBGEN - Debug Actions Enable
These bits allow the counter channel to perform certain actions in response to the chip entering debug
mode.
Table 20-9. Values for DBGEN
Value
00
01
10
11
Meaning
Continue with normal operation during debug mode. (default)
Halt channel counter during debug mode.
Force OFLAG to logic 0 (prior to consideration of the OPS bit) during debug mode.
Both halt counter and force OFLAG to 0 during debug mode.
20.4.3.11 Status Register (STS)
eTimer_CHNL ₀
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
_BASE + $14
Read
000000
WDF RCF ICF2 ICF1 IEHF IELF TOF
TCF
Write
Reset
0000000000000000
Figure 20-13. Status Register (STS)
WDF - Watchdog Time-out Flag
20-14
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor