PXS20RM Datasheet, PDF (390/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

eDMA Channel Mux (DMA_MUX)
configuration registers in the PIT. Please refer to the Periodic Interrupt Timer Block Guide for more
information on this topic.
NOTE
Because of the dynamic nature of the system (i.e. DMA channel priorities,
bus arbitration, interrupt service routine lengths, etc.), the number of clock
cycles between a trigger and the actual DMA transfer cannot be guaranteed.
Source #1
Source #2
Source #3
Trigger #1
Trigger #2
DMA Channel #0
Source #27
Always #1
Trigger #4
DMA Channel #3
Always #4
Figure 18-3. DMA_MUX triggered channels
The DMA channel triggering capability allows the system to “schedule” regular DMA transfers, usually
on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by
gating the request from the Peripheral to the DMA until a trigger event has been seen. This is illustrated
in Figure 18-4.
18-6
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor