PXS20RM Datasheet, PDF (1035/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

LIN Controller (LINFlexD)
Table 31-43. TCD settings (master node, RX mode)
TCD field
CITER[14:0]
BITER[14:0]
NBYTES[31:0]
SADDR[31:0]
SOFF[15:0]
SSIZE[2:0]
SLAST[31:0]
DADDR[31:0]
DOFF[15:0]
DSIZE[2:0]
DLAST_SGA[31:0]
INT_MAJ
D_REQ
START
Value
1
1
[4] + 4/8 = N
BIDR address
4
2
–N
RAM address
4
2
–N
0/1
1
0
Description
Single iteration for the “major” loop
Single iteration for the “major” loop
Data buffer is stuffed with dummy bytes if the length is not
word aligned.
BIDR + BDRL + BDRM
Word increment
Word transfer
Word increment
Word transfer
No scatter/gather processing
Interrupt disabled/enabled
Only on the last TCD of the chain.
No software request
31.11.3 Slave node, TX mode
On a slave node in TX mode, the DMA interface requires a DMA TX channel for each ID filter
programmed in TX mode. In case a single DMA TX channel is available, a single ID field filter must be
programmed in TX mode. Each TCD controls a single frame, except for the extended frames (multiple
TCDs). The memory map associated to the TCD chain (RAM area and LINFlexD registers) is shown in
Figure 31-47.
TCD (n)
RAM area
BDRL + BDRM
(4/8 bytes)
DMA transfer
LINFlex2 registers
BDRL + BDRM
(4/8 bytes)
Frame (n)
Slave –> Master
Slave –> Slave
TCD (n+1)
Linked chain
BDRL + BDRM
(8 bytes)
BDRL + BDRM
(8 bytes)
Extended
Frame (n+1)
TCD (n+2)
BDRL + BDRM
(4/8 bytes)
BDRL + BDRM
(4/8 bytes)
Extended
Frame (n+2)
1 DMA TX channel/filter (TCD single and/or linked chain)
Figure 31-47. TCD chain memory map (slave node, TX mode)
The TCD chain of the DMA Tx channel on a slave node supports:
Freescale Semiconductor
PXS20 Microcontroller Reference Manual, Rev. 1
31-59