PXS20RM Datasheet, PDF (568/1368 Pages) Freescale Semiconductor, Inc – PXS20 Microcontroller

Flash Memory
Priority level
1
2
3
4
Table 23-4. MCR bit set/clear priority levels
MCR bit(s)
ERS
PGM
EHV
ESUS, PSUS
If the user attempts to write two or more MCR bits simultaneously then only the bit with the lowest priority
level is written. Setting two bits with the same priority level is prevented by existing write locks or do not
put the flash in an illegal state.
For example, setting ERS and PGM simultaneously results in only ERS being set. Attempting to clear
EHV while setting PSUS results in EHV being cleared, while PSUS is unaffected.
23.1.6.2 Low/Mid Address Space Block Locking Register (LML)
The Low/Mid Address Block Locking Register (LML) provides a means to protect blocks from being
modified. These bits, along with bits in the Secondary LLOCK (SLL), determine if the block is locked
from program or erase. An “OR” of LML and SLL determine the final lock status.
NOTE
A reset value of 1* in Figure 23-4 indicates that the reset value of these
registers is determined by Flash values in the shadow block. An erased
shadow block causes the reset value to be 1.
Offset 0x0004
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R _LME
0
0
0
0
0
0
0
0
0
0 SLOCK 0
0
MLOCK
W
RESET: ₀
0
0
0
0
0
0
0
0
0
0
1*
0
0
1*
1*
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R₀
0
0
0
0
0
LLOCK
W
RESET: ₀
0
0
0
0
0
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
= Unimplemented or Reserved
Figure 23-4. LML Register
LML register functions are shown in Table 23-5.
23-18
PXS20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor